1. Field of the Invention
The present invention relates to electronic circuits, and more particularly, to circuits for protection against electrostatic discharge (ESD). 2. Background
In order to protect solid state integrated circuits against electrostatic discharge, a variety of ESD protection circuits have been designed which absorb the energy of the electrostatic discharge, thereby protecting the integrated circuits from damage resulting from the high voltage pulses of the electrostatic discharge. A conventional circuit for ESD protection typically occupies a large surface area in an integrated circuit chip because it has very large transistor components. For example, large N-channel field effect transistors (NFETs) have been implemented as clamps in conventional circuits for ESD protection to absorb the high voltage, short duration pulses of electrostatic discharge. However, because of the large size of the transistors, conventional circuits for ESD protection are usually non-synthesisable with the integrated circuit which it is designed to protect. Furthermore, a conventional circuit for ESD protection with a large NFET clamp needs an N-well resistor connected to the drain of the NFET. Variations of the N-well resistor values due to uncertainties in existing foundry processes may cause ESD failures in conventional circuits with large NFET clamps.
The present invention provides an electrostatic discharge (ESD) protection circuit, roughly comprising:
a P-channel field effect transistor (PFET) having a source capable of receiving a source voltage at a source input that is susceptible to electrostatic discharge, a drain that is grounded, and a gate capable of receiving either a high voltage to turn off the PFET or a low voltage to turn on the PFET;
a buffer connected to the gate of the PFET; and
a damping network connected to the buffer.
Advantageously, the ESD protection circuit in an embodiment according to the present invention is capable of providing improved protection against ESD failure for integrated circuits. Furthermore, the ESD protection circuit in an embodiment according to the present invention is highly area efficient and fully synthesisable with the integrated circuit which it is designed to protect from electrostatic discharge.